Standard semiconductor cell fabrication is a method for designing integrated circuits for specific applications. Circuits are designed based on the desired functions using cells from a cell library which are combined and constructed by a placement tool to result in the desired circuits. Standard semiconductor cell library performance is limited by the current a transistor of a cell can deliver. This is proportional to the width of the transistor so it is desirable to enable the transistor to be as wide as possible in a standard cell to deliver high performance circuits.
A typical standard cell loses some active area in two regions including the power rail and the center of the cell where signal connection is performed. In FINFET technologies where the pitch of the FIN is usually fixed, the width of the power rail must be able to fit within a small number of FIN to limit the performance loss when a whole FIN is lost.
Accordingly, a need exists for improved systems and methods for minimizing the area loss in the power rail for high density standard cell for planar and FINFET integrations.